1. Field of the Invention
The invention is directed to a package substrate structure and more particularly, to a package substrate structure capable of forming patterned circuit layers by directly electroplating a selective-electroplating epoxy compound thereof.
2. Description of Related Art
In the information society nowadays, people tend to rely on electronic products more and more. To meet with the requirements of high speed, high performance, and being light, thin, and compact on the electronic products nowadays, flexible circuit boards having flexibility are more commonly applied in various electronic products, such as mobile phones, notebook PCs, digital cameras, tablet PCs, printers, and disk players, etc.
Generally speaking, in production of a package structure, a preprocessing process, a sputtering process, a copper-laminating or copper-plating process and a pholithography process are performed on one or two opposite surfaces of an insulation substrate to form circuit layers thereon. However, the processes in the manufacturing method are complicated and the cost of sputtering is relatively high. Moreover, it is challenging for a patterned circuit layer formed by using a patterned dry film as an electroplating barrier to meet the requirement of fine pitch nowadays. Moreover, the insulation layer is typically made of a polyimide or an Ajinomoto build-up film (ABF) resin, which costs higher. Therefore, the package structures are currently manufactured in complicated processes with high cost.
Besides, in order to increase circuit density of a package insulation substrate, a silicon chip is commonly employed as the insulation substrate in the industry. However, a manufacturing process for a silicon insulation substrate is complicated and has to go through complicated processes such as polishing process in a chip fab, long-term deep etching of conductive vias, washing, oxidation, sputtering, plating, photoresist covering, exposure, development, etching, washing, oxidation, photoresist covering, exposure, development, etching and washing, etc. A thickness of the silicon insulation substrate is generally at least 200μ. Such thickness has difficulty in reduction due to structural brittleness and limitations of the manufacturing process, which leads to incapability of effectively reducing overall thickness of a package structure using the package substrate and to higher cost due to the complicated processes. Moreover, in the two types of package insulation substrates, connection circuits are formed by a stacking process and thus, formed on surfaces of insulation dielectric layers.
Accordingly, how to form patterned circuit layers on a insulation material by selectively electroplating the same and how to apply the technique to the package structures have become one of the issues to be resolved for the industry.